Avago
28nm, 40nm, 65nm, 90nm Avago SerDes Solutions from eSilicon
Now available from eSilicon: Avago Technologies’ industry-proven, best-in-class SerDes cores. Avago’s SerDes, combined with eSilicon’s proven design, manufacturing and productization services, provides a compelling combination for the development and volume production of custom chips for growing markets such as storage, communications, and high-performance computing markets.
 |
|
 |
| Figure 1: Pre-DFE Rx Eye Measurement |
|
Figure 2: Post-DFE Rx Eye Measurement
|
| Images provided by Avago Technologies, 10.3125 Gbps backplane DFE operation. Channel description: 26cm char board, >1 meter over FR4 backplane, two backplane connectors. |
Avago SerDes Overview
Avago SerDes cores support a broad range of popular industry standards such as PCI-Express, Fibre Channel, QPI, CEI, Interlaken, 10GBASE-KX/KX4/KR, FCoE, GigE, XAUI, XFI/SFI, and SAS/SATA and are suitable for both chip-to-chip and backplane applications. The cores feature high data rates of up to 28Gbps. The SerDes cores offer extremely low jitter, making it possible to integrate hundreds of SerDes channels on a single chip.
Avago’s SerDes cores are based on a modular, multi-rate architecture allowing hundreds of SerDes channels to be easily integrated on a single chip. The SerDes cores include a unique decision feedback equalization (DFE) feature resulting in a number of key performance differentiators such as low overall power, best-in-class data latency, and best-in-class jitter and crosstalk tolerance.
Avago SerDes Protocols
Standard
|
|
Link Rate (Gbps)
|
90nm
|
65nm
|
40nm
|
28nm
|
| PCI-Express (PCIe) |
G1, G2 |
2.5 (G1), 5.0 (G2) |
✔ |
✔ |
✔ |
✔ |
| |
G3 |
8.0 (G3) |
- |
- |
- |
✔ |
| Fibre Channel |
1GFC, 2GFC, 4GFC, 8GFC |
1.0625, 2.125, 4.25, 8.5 |
(>8G) |
✔ |
✔ |
✔ |
| |
16GFC (15GFC-EL Only) |
14.025 |
- |
- |
- |
✔ |
| |
10GFC |
10.5188 |
- |
✔ |
✔ |
✔ |
| Ethernet |
Interlaken 6G, 11G |
|
- |
✔ |
✔ |
✔ |
| |
FCoE (10G FC) |
|
- |
✔ |
✔ |
✔ |
| |
GigE, XAUI |
1.25G, 3.125 (x4 lanes) |
✔ |
✔ |
✔ |
✔ |
| |
10G-Base LR, SR |
|
- |
✔ |
✔ |
✔ |
| |
10GBASE-KX/KX4/KR |
1.25, 3.125, 10.3125 |
- |
✔ |
✔ |
✔ |
| |
XFI / SFI |
10.3125 |
- |
✔ |
✔ |
✔ |
| |
802.3ba |
40 (4x10G), 100 (10x10G) |
- |
- |
- |
✔ |
| |
802.3az |
1.25, 3.125, 10.3125 |
- |
- |
✔ |
✔ |
| Custom |
5G, 6.25G, 7.5G |
5G, 6.25G, 7.5G |
(>7G) |
(>7G) |
✔ |
- |
| |
12.5G - 14G Backplane |
12.5G, 14G |
- |
- |
(>14G) |
- |
| |
2 - 25G |
2 Ð 25G |
- |
- |
- |
✔ |
| CEI |
CEI-6G |
6.25 (LR & SR; MR) |
✔ |
✔ |
✔ |
✔ |
| |
CEI-11G |
11 (LR & SR) |
- |
✔ |
✔ |
✔ |
| |
CEI-25G |
28 (SR), 25 (LR) |
- |
- |
- |
✔ |
| QPI |
QPI |
3.2G to 9.6G |
✔ |
- |
✔ |
- |
| SAS/SATA |
1, 2 |
3G, 6G |
✔ |
- |
- |
- |
Product Features
Now available in TSMC 28nm, 40nm, 65nm and 90nm, these SerDes cores represent Avago’s ninth generation of production-proven, high-performance, multi-rate transceivers with best-in-class features such as:
- Rates from 1Gbps up to 28Gbps
- Robust performance due to noise reduction circuitry, powerful DFE, continuous time linear equalizer (CTLE), and transmit equalization
- Bit-error rate (BER) of less than 10-17
- Targeted for operation over tough backplanes (>30 dB of insertion loss at 10.3125 Gbps)
- Optional proprietary encoding schemes
- Meets established industry standards such as PCI-Express, Fibre Channel, QPI, CEI, Interlaken, 10GBASE-KX/KX4/KR/CX4, FCoE, GigE, XAUI and XFI/SFI
- More than 300 SerDes channels per die
- Advanced on-chip diagnostic intelligence
eSilicon SerDes Integration Experience
eSilicon makes it easy to integrate a wide range of data rates and a variety of protocols in their custom ASIC flow with the use of Avago Technologies’ high-performance multi-rate transceivers and an extensive portfolio of specialty third-party semiconductor intellectual property (IP). Avago Technologies’ low-power slim design with state-of-the-art jitter performance allows integration of over 300 channels on a single chip for low-cost server or networking system solutions using existing backplanes while maintaining the same power budget
Avago SerDes Availability
eSilicon, through its agreement with Avago Technologies, offers a broad portfolio of SerDes cores for a variety of data rates and protocol standards. Now you can select the right interface standard at the right speed in a given process node in order to build your own custom chip solution.
If you would like more information on these offerings, or have questions about other IP not featured here,
This e-mail address is being protected from spambots. You need JavaScript enabled to view it
eSilicon has an extensive database of IP and can help find the right IP for your custom chip.