White Paper

High-Performance Classification Using Embedded Ternary Content Addressable Memory (TCAM)

With port speeds exceeding 100Gbps, route lookups that are a fundamental application to all routers have relied on ternary content addressable memories (TCAM) to provide a lookup response within a clock cycle. However, these devices in “discrete form” suffer from limitations in terms of power, cost and real estate and to some extent lack the required flexibility. Embedding a TCAM block along with the rest of the system in a single device should overcome these disadvantages. This paper provides an overview of advantages of embedded TCAMs and describes a few applications that could take advantage of embedded TCAM technology. [View more white papers]

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Home WHAT Custom IP Multi-Port Register File

Specialty Register Files

Multi-Port Register Files

eSilicon has designed four-port register file memory compilers catering to multiple customers in the networking and communications domains. These memories have two write ports and two read ports.

eSilicon four-port register files are silicon proven in 65nm and 40nm geometries. Our 28nm four-port register file is available now.

Networking and communications customers have long relied on the performance of eSilicon's high-speed register files to meet the demanding wireline speed requirements of their tier-one customers.

Asynchronous Register File

eSilicon has designed asynchronous register file memory compilers catering to multiple customers in the networking and communications domains. These memories have one synchronous write port and one asynchronous read port.

Our 28nm asynchronous register file is available now.

eSilicon's philosophy for developing memories is to customize the specialty register file memory compilers, such as four-port register files and asynchronous register files, to end-customer requirements. This usually involves turning multiple knobs to tune the area, power, performance of register files per customer application requirements. The chart below shows some of the elements that eSilicon has successfully used in the past to meet customer targets.

Area

Performance

Power Management

Testability

Functional Options

  • Aspect Ratio
  • Side Decode
  • Low Vt for Highest Performance
  • Banking
  • Center Decode
  • DVFS
  • Mixed Vt Periphery
  • BIST Mux
  • Scan Flops
  • Synchronous Bypass
  • Read Stress
  • Write Stress
  • Column Redundancy
  • Row Redundancy
  • Bit Write

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